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NTD60N02R
Power MOSFET
62 A, 25 V, N?Channel, DPAK
Features
?
?
?
?
?
Planar HD3e Process for Fast Switching Performance
Low R DS(on) to Minimize Conduction Loss
Low C iss to Minimize Driver Loss
Low Gate Charge
Optimized for High Side Switching Requirements in
V (BR)DSS
25 V
http://onsemi.com
R DS(on) TYP
8.4 m W @ 10 V
I D MAX
62 A
High?Efficiency DC?DC Converters
?
Pb?Free Packages are Available
N?Channel
D
MAXIMUM RATINGS (T J = 25 ° C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain?to?Source Voltage
Gate?to?Source Voltage ? Continuous
V DSS
V GS
25
± 20
Vdc
Vdc
G
Thermal Resistance
Junction?to?Case
Total Power Dissipation @ T C = 25 ° C
Drain Current
Continuous @ T C = 25 ° C, Chip
Continuous @ T C = 25 ° C, Limited by Package
Continuous @ T A = 25 ° C, Limited by Wires
Thermal Resistance
Junction?to?Ambient (Note 1)
Total Power Dissipation @ T A = 25 ° C
Drain Current ? Continuous @ T A = 25 ° C
R q JC
P D
I D
I D
I D
R q JA
P D
I D
2.6
58
62
50
32
80
1.87
10.5
° C/W
W
A
A
A
C/W
W
A
4
1 2
3
CASE 369AA
DPAK
S
4
1
2 3
CASE 369AC
3 IPAK
4
1
2
3
CASE 369D
DPAK
Thermal Resistance
Junction?to?Ambient (Note 2)
Total Power Dissipation @ T A = 25 ° C
Drain Current ? Continuous @ T A = 25 ° C
Operating and Storage Temperature
R q JA
P D
I D
T J , and
T stg
120
1.25
8.5
?55 to
175
° C/W
W
A
° C
(Surface Mount) (Straight Lead) (Straight Lead)
STYLE 2 STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENTS
Single Pulse Drain?to?Source Avalanche Energy
? Starting T J = 25 ° C
(V DD = 50 Vdc, V GS = 10.0 Vdc,
I L = 11 Apk, L = 1.0 mH, R G = 25 W )
Maximum Lead Temperature for Soldering
Purposes, 1/8 ″ from case for 10 seconds
E AS
T L
60
260
mJ
° C
4
Drain
4
Drain
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 0.5 in sq drain pad size.
1
Gate
2
Drain
3
Source
1 2 3
Gate Drain Source
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
Y
WW
T60N02R
G
= Year
= Work Week
= Device Code
= Pb?Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
? Semiconductor Components Industries, LLC, 2006
December, 2006 ? Rev. 12
1
Publication Order Number:
NTD60N02R/D
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